As a non-volatile semiconductor storage device, a ferroelectric memory (ferroelectric random access memory: FeRAM) that uses a ferroelectric material as a capacitor is known. Ferroelectric memories are categorized into a 1T1C type in which data is read by comparing a reference signal and a signal from one memory cell constituted of a transistor and a ferroelectric capacitor, and a 2T2C type in which data is read by comparing complementary signals from a set of two memory cells (hereinafter referred to as complementary reading). In recent years, storage devices in which a 1T1C memory region and a 2T2C memory region coexist are known (Japanese Patent Application Laid-Open Publication No. 2016-54012, for example).
In a semiconductor memory such as a ferroelectric memory, a plurality of bit lines are provided in parallel with each other. As a result, when reading from the memory, adjacent bit lines interfere with each other, resulting in noise between the bit lines. This noise between the bit lines results in a decrease in the reading margin. In order to prevent a decrease in reading margin, a semiconductor memory was conceived of in which noise is evenly distributed among bit lines by a configuration in which bit lines forming a pair intersect with each other and other adjacent pairs of bit lines are at the same parallel distance (Japanese Patent Application Laid-Open Publication No. S63-237290, for example). Also, a method was conceived of in which bit lines adjacent to a selected bit line are deselected and kept at ground potential, thereby preventing noise between bit lines (Japanese Patent Application Laid-Open Publication No. 2001-135077, for example).